16.5.3 Interrupt Enable Register

This register enables the COMMS_INT to be set whenever the corresponding bit is set in the Table 16-4 register.

Table 16-5. INT_ENABLE
Bit Number	Name	R/W	Reset Value	Description
[7:0]	ENABLE	R/W	0x00	Matches corresponding bit in status register 0: Disables Interrupt
				1: Enables Interrupt

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