8.2.1.2.1 Ping-Pong Mode

Ping-pong mode is a dual buffering scheme for continuous stream of operation. There are two buffers (Buffer A and Buffer B) associated with each DMA channel for ping-pong operation. This removes the real-time constraint on the firmware of having to service the DMA channel in real-time, which might exist if there is only one DMA buffer per channel.

To begin a transaction, source address, destination address, and transfer size in bytes of buffer A and buffer B are to be configured by the AHB bus matrix master (such as, Cortex-M3 firmware). The following figure shows the sequence of operations that must be performed by firmware for ping-pong operation on a configured DMA channel. The channel control register (Table 8-7) is configured initially before enabling ping-pong operation.