11.6.11.1 Interrupt Enable Register
The interrupt enable register controls which particular bits from the interrupt status register are used to assert the interrupt output int_n. See Interrupt Generation for more details. The bits in the INT_ENABLE register control which bits in the INT_STATUS register are used to enable the final output, int_n, interrupt. The int_n interrupt is asserted if a particular interrupt status bit and the respective enable bit are set. The following table provides the INT_ENABLE register bit descriptions.
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:16] | Reserved | 0 | Reserved |
| 15 | sst_failure_enbl | 0 | Single-shot transmission failure interrupt enable. |
| 14 | stuck_at_0_enbl | 0 | Stuck at dominant error interrupt enable. |
| 13 | rtr_msg_enbl | 0 | RTR auto-reply message sent interrupt enable. |
| 12 | rx_msg_enbl | 0 | Receive message available interrupt enable. |
| 11 | tx_msg_enbl | 0 | Message transmitted interrupt enable. |
| 10 | rx_msg_loss_enbl | 0 | Received message lost interrupt enable. |
| 9 | bus_off_enbl | 0 | Bus off interrupt enable. |
| 8 | crc_err_enbl | 0 | CRC error interrupt enable. |
| 7 | form_err_enbl | 0 | Format error interrupt enable. |
| 6 | ack_err_enbl | 0 | Acknowledge error interrupt enable. |
| 5 | stuff_err_enbl | 0 | Bit stuffing error interrupt enable. |
| 4 | bit_err_enbl | 0 | Bit error interrupt enable. |
| 3 | ovr_load_enbl | 0 | Overload message detected interrupt enable. |
| 2 | arb_loss_enbl | 0 | Arbitration loss interrupt enable. |
| 1 | Reserved | 0 | Reserved |
| 0 | Int_enbl | 0 | Global interrupt enable flag. 0: All interrupts are disabled 1: Enabled interrupt sources are available |