6.1.3.1.1 Arbitration Parameters

The following slave arbitration configuration parameters are user programmable registers in the SYSREG block.

• Programmable slave maximum latency: Slave maximum latency, ESRAM_MAX_LAT, decides the peak wait time for a fixed priority master arbitrating for eSRAM access while the WRR master is accessing the slave. After the defined latency period, the WRR master will have to re-arbitrate for slave access. Slave maximum latency can be configurable from 1–8 clock cycles (8 by default). ESRAM_MAX_LAT is only supported for fixed priority masters addressing eSRAM slaves; it has no effect on WRR masters. The system designer can use this feature to ensure the processor latency for accesses to eSRAM is limited to a defined number of clock cycles. This is to facilitate limiting the ISR latency for real-time-critical functions.
• Programmable weight: MASTER_WEIGHT0_CR and MASTER _WEIGHT1_CR are 5-bit programmable registers located in the SYSREG block. These registers define the number of consecutive transfers the weighted master can perform without being interrupted by a fixed priority master, or before moving onto the next master in the WRR cycle.