6.1.3.1.2 Pure Round Robin Arbitration
This is the default arbitration mode after reset. The programmable weight value of each master is set to 1, and ESRAM_MAX_LAT = 1.
The arbitration scheme for each slave port is identical in pure round robin arbitration, as shown in the following figure. The processor masters have priority over the non-processor masters. Each non-processor master accessing a slave has equal priority on a round robin basis. However, if a locked transaction occurs, the master issuing the lock maintains ownership of the slave until the locked transaction completes.
The following table gives an example of a pure round robin and fixed priority arbitration scenario for eSRAM1. This example illustrates default AHB bus matrix behavior.
| Master | HCLK | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | |
| M3-I: M0 | — | — | — | eSRAM1 | — | — | — | — | — |
| M3-D: M1 | — | — | — | eSRAM1 | — | — | — | — | — |
| M3-S: M2 | — | eSRAM1 | — | — | eSRAM1 | — | — | — | — |
| HPDMA: M3 | eSRAM1 | — | — | — | — | — | — | — | — |
| FIC_0: M4 | eSRAM1 | — | — | — | — | — | — | — | — |
| FIC_1: M5 | eSRAM1 | — | — | — | — | — | — | — | — |
| GIGE: M6 | eSRAM1 | — | — | — | — | — | — | — | — |
| PDMA: M7 | eSRAM1 | — | — | — | — | — | — | — | — |
| eSRAM1: S1 | HPDMA M3 | M3-S M2 | FIC_0 M4 | M3-D M1 | M3-I M0 | M3-S M2 | FIC_1 M5 | TSE M6 | PDMA M7 |
In the preceding table, WRR masters and fixed priority masters arbitrate for the S1 (eSRAM1) slave during HCLK cycle 1. The last row in the table, labeled eSRAM1: S1, shows which of the masters obtains access to the slave according to the arbitration in that clock cycle. In the first cycle, master M3 (HPDMA) is granted access, since it is the first master in the round robin scheme. In the second cycle, even though master M4 is scheduled to get access to the slave as per the round robin scheme, the M2 master (Cortex-M3 processor SBus) is granted access since it has a higher priority. In the third cycle, the master M4 (FIC_0) in the round robin scheme is granted access. In the fourth cycle, both M0 (Cortex-M3 processor ICode bus) and M1 (Cortex-M3 processor DCode bus) are trying for access. Since M1 has the highest priority among the fixed priority masters, it is granted access, followed by the M0 master. WRR masters are delayed while the fixed priority masters get access to the slave. The remaining cycles are consumed by the WRR masters in order.