6.1.3.1.4 Arbitration for eSRAM Slaves

For eSRAM slaves, the maximum latency seen by the Cortex-M3 processor bus masters can affect overall system performance. To manage this latency, a programmable maximum latency parameter, SW_MAX_LAT_ESRAM<0/1>, is available to optimize arbitration for the eSRAM slaves from a fixed priority master. The parameter SW_MAX_LAT_ESRAM_<0/1> sets a ceiling as to the number of cycles the Cortex-M3 processor bus master, or any fixed priority master, has to wait before accessing an eSRAM slave that is currently being accessed by a WRR master. When a WRR master has a programmable weight greater than the SW_MAX_LAT_ESRAM<0/1> value, the WRR master will have to re-arbitrate for the slave after SW_MAX_LAT_ESRAM<0/1> cycles. The following equation gives the maximum latency seen by a processor master while accessing an eSRAM slave:

Maximum latency seen by the Cortex-M3 processor master = min {programmable weight (WRR master), SW_MAX_LAT_ESRAM<0/1>}

For example, if SW_WEIGHT_HPDMA is set to 18 and SW_MAX_LAT_ESRAM0 is set to 4, then the maximum latency is min {18, 4} = 4. Similarly, if SW_WEIGHT_PDMA is set to 2 and SW_MAX_LAT_ESRAM1 is set to 6, then the maximum latency is min {2, 6} = 2. The following table depicts a typical scenario.

In this scenario, the slave maximum latency is set to 4 and the master programmable weight is set to 8, so the maximum latency seen by the processor bus master is min {4, 8} = 4. When the WRR master starts transactions with the eSRAM slave, it can perform a number of transactions equal to the programmed maximum latency or the programmed weight, whichever is less, before re-arbitrating for the slave.