16.5.6 Frame/Command Byte Register
This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO. If the Transmit FIFO is full at the time of a write, an OVERFLOW will be set in the Table 16-4 register. Similarly, if Receive FIFO is empty at the time of a read, an UNDERFLOW will be generated.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [7:0] | FRAME_START8 | R/W | 0x00 | Write: Writes byte to the MSS COMM_BLK transmit FIFO Read: Read a byte from the MSS COMM_BLK receive FIFO |
When the FRAME_START8 register is written, the command bit (Bit 8 on DATA) is set to 1, indicating the start of a frame, that is, the command byte. Writes to this register automatically set the SIZETX to 0 (1 byte), and reads set the SIZERX to 0 (1 byte). The Table 16-4 register bit 7 indicates that this byte is a command.