16.5.2 Status Register
This register provides status information. R/W bits are cleared by writing 1. FIFO empty full flags automatically clears as FIFO is full and empty.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 7 | COMMAND | R | 0 | First byte queued in receive FIFO has the command marker set |
| 6 | SIIERROR | R/W | 0 | When an SII transfer (MSS to SII) is in progress, the start of frame marker is set on one or more of the bytes. Write 1 to clear |
| 5 | FLUSHRCVD | R/W | 0 | Indicates that a FLUSH has been received. Write 1 to clear |
| 4 | SIIDONE | R/W | 0 | Indicated that the transfer to SII Bus is complete. Write 1 to clear |
| 3 | UNDERFLOW | R/W | 0 | Receive Overflow. Indicates that the receive FIFO was read when empty. Write 1 to clear |
| 2 | OVERFLOW | R/W | 0 | Transmit Overflow. Indicates that the Transmit FIFO was written when full. Write 1 to clear |
| 1 | RCVOKAY | R | 0 | RCV FIFO non empty. Indicates that 1 or 4 bytes may be read based on SIZERX. |
| 0 | TXTOKAY | R | 1 | TXT FIFO non full. Indicates that 1 or 4 bytes may be written depending on SIZETX. |
Important: The System IP Interface (SII) master connects the
System Controller with all the internal elements. It is used to transfer data to and from
the MSS memory space by the System Controller for System Services. It is also used for
factory test but not available for customer.