16.5.7 Frame/Command Word Register
This register writes a word (32-bits) to the Transmit FIFO or reads a word from the Receive FIFO. If the Transmit FIFO has less than four spaces available at the time of a write, an OVERFLOW will be set in Table 16-4 register. Similarly, if Receive FIFO has less than four bytes available at the time of a read, an UNDERFLOW will be generated.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:0] | FRAME_START32 | R/W | 0x00000000 | Write: Writes a word to the MSS COMM_BLK transmit FIFO Read: Reads a word from the MSS COMM_BLK receive FIFO |
The Least Significant Bit (LSB) is transferred on the DATA bus first. When the Table 16-9 register is written, the command bit is set to 1, indicating the start of a frame, that is, command byte. The command bit (Bit 8 on DATA) will be set on the first byte for writes.
Writes to this register automatically sets the SIZETX to 1 (4 bytes) and reads set the SIZERX to 1 (4 bytes). The Table 16-4 register bit 7 indicates that this word is a command.