16.5.4 Byte Data Register
This register writes a byte to the Transmit FIFO or reads a byte from the Receive FIFO. If the Transmit FIFO is full at the time of a write, an OVERFLOW will be set in the STATUS register. Similarly, if Receive FIFO is empty at the time of a read, an UNDERFLOW will be generated.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [7:0] | DATA8 | R/W | 0x00 | Write: Writes a byte to the MSS COMM_BLK Transmit FIFO Read: Reads a byte from the MSS COMM_BLK Receive FIFO |
When the Table 16-6 register is written, the command bit (Bit 8 on DATA) is set to 0, indicating that it is data. Writes to this register automatically set the SIZETX to 0 (1 byte), and reads set the SIZERX to 0 (1 byte).