16.5.5 Word Data Register
This register writes a word (32 bits) to the Transmit FIFO or reads a word from the Receive FIFO. If the Transmit FIFO has less than 4 spaces available at the time of a write, an OVERFLOW will be set in the Table 16-4 register. Similarly, if Receive FIFO has less than 4 bytes available at the time of a read, an UNDERFLOW will be generated.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:0] | DATA32 | R/W | 0x00000000 | Write: Writes a word to the MSS COMM_BLK Transmit FIFO Read: Read a word from the MSS COMM_BLK Receive FIFO |
The LSB is transferred on the DATA bus first. When the Table 16-7 register is written, the command bit (Bit 8 on DATA) is set to 0, indicating that it is data. Writes to this register automatically set the SIZETX to 1 (4 bytes) and reads set the SIZERX to 1 (4 bytes).