23.2.2 Master Identity Port to the Fabric

The AHB bus matrix provides a 2-bit side band signal to the FPGA fabric (one 2-bit signal per FIC instance). The side band signal indicates to the slave, which is implemented in the FPGA fabric, the identification of the master performing the current transaction. These signals have the same timing as other AHB Lite master signals, such as HTRANS, HMASTLOCK and so on. Table 23-2 provides the decoding of the master accessing the FPGA fabric slave through the MSS AHB bus matrix.

The Libero SoC MSS configurator allows exposure of the master ID port; if the interface is selected to act as a master of the FPGA fabric.