23.2.1 Configure FIC in Bypass Mode or Synchronous Pipelined Mode

You can configure FIC_0 and FIC_1 individually through the Libero SoC MSS configurator. The AHB-Lite configuration in the FIC configurator provides the Use Bypass Mode option to enable or disable the address and data pipelining between FPGA fabric logic and the AHB bus matrix. In some scenarios, the FPGA fabric logic needs to access the MSS peripherals (such as eSRAM or eNVM) with very high throughput. In such cases, the FPGA fabric logic should be connected to the FIC using an AHB-Lite interface.

In bypass mode (non-pipelined mode / Use Bypass Mode option checked), it is possible to achieve zero-wait state access between the FPGA master and a zero-wait state capable MSS slave, if there is no other master accessing that slave. However, the setup time requirement of the FIC interface is a bigger, which may lower the overall frequency of operation. The clock ratio between M3_CLK, FIC_0_CLK, and FIC_1_CLK must be set to 1:1 when bypass mode is selected. This requirement is enforced in the MSS CCC configurator when bypass mode is selected.

In Pipelined mode (Use Bypass Mode option unchecked / default mode), the interface between the AHB bus matrix and FPGA has registered signals that reduce setup requirements.This may improve overall system frequency, but these registers introduce a bubble in the AHB transaction pipe. It results in inserting a wait-state for each transaction even if the Master and Slave are capable of zero-wait state access. Relative clock frequency between the MSS clock, M3_CLK, and the fabric clock for Synchronous Pipelined mode can be 1:1, 2:1, 4:1, 8:1, 16:1, or 32:1.

You have to analyze the critical paths between the FIC and the logic in the FPGA fabric, when Use Bypass Mode is enabled. You need to make sure that all the timing requirements have been met between FIC and FPGA fabric logic.

FIC32_0_DIVISOR[2:0] and FIC32_1_DIVISOR[2:0] configuration inputs from the SYSREG block MSSDDR_FACC1_CR configuration register, specify the ratio of clocks between the MSS system clock, M3_CLK, and the fabric clock used by the soft IP interfacing with FIC_0 and FIC_1. The FAB0_AHB_BYPASS and FAB1_AHB_BYPASS fields from the SYSREG block FAB_IF_CR register, configure FIC_0 and FIC_1 in Bypass mode or Synchronous Pipelined mode.