13.2.4.4.1 RX Overflow

An Rx overflow condition arises when the receive FIFO has not been emptied in time. As a result, the last write to the receive FIFO from the channel, overwrites the data that is received earlier and which is not read by the host processor. Eventually, the FIFO fills up and subsequent writes by the channel cause the Rx to overflow. The corrective action for the bus master is to read from the FIFO until the FIFO is empty. This can be checked by reading the FIFO status in the Table 13-11 register.