13.4.3.10 SPI Raw Interrupt Status Register
The following table describes the Raw Interrupt Status (RIS) register. This register returns the current raw status value, prior to masking, of the corresponding interrupt.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:6] | Reserved | R/W | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 5 | SSEND | R/W | Indicates that SPI_X_SS[x] has gone inactive. | |
| 4 | CMDINT | R/W | Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames (SPI_X_SS[x] held active). | |
| 3 | TXCHUNDR | R | 0 | RAW interrupt status. Reading this returns raw interrupt status. Raw status of transmit channel under-run |
| 2 | RXCHOVRF | R | 0 | Raw status of receive channel overflow |
| 1 | RXRDY | R | 0 | Receive data ready (data received in FIFO) |
| 0 | TXDONE | R | 0 | Raw status of transmit done (data shifted out) |