5.2.2.1 SECDED-ON

SECDED mode can be turned ON by configuring the Table 5-21 register. The total available memory for each eSRAM in this mode is 32 KB. The eSRAM controller generates 7 check bits for every 32 bits of data, so for every 32 bits of data there will be 7 bits of encoded data. The 7 bits of ECC allow 1-bit correction and 2-bit detection on the user data and ECC field. The 32 data bits and 7 bits of ECC are written to the memory with zero wait states. Byte and half-word write operations are done using a 
read-modify-write operation. The read-modify-write operation requires an additional wait state for byte and half-word write operations.

For a 1-bit error, the previous 32 bits of data and ECC value are read and corrected automatically. The complete 32 bits plus ECC is rewritten. For byte and half-word write operations, there is one wait state required as the ECC value is read and corrected for the byte/half-word.

When a 2-bit error is detected during a read cycle for 32-bit data, HRESP is asserted High for two clock cycles and at the same time HREADYOUT goes Low for one clock cycle to indicate an error.

When a 2-bit error is detected during the read part of a read-modify-write byte or half-word operation, HRESP is asserted High.