21.5.23 GPIO System Reset Control Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:4] | Reserved | 0 | |
| 3 | MSS_GPIO_31_24_SYSRESET_SEL | 0 | 0: Selects the combination of either
power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric to reset the GPIO 1: Causes GPIO[31:24] to be held in reset by the soft reset signal MSS_GPIO_31_24_SOFT_RESET |
| 2 | MSS_GPIO_23_16_SYSRESET_SEL | 0 | 0: Selects the combination of either
power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric to reset the GPIO 1: Causes GPIO[23:16] to be held in reset by the soft reset signal MSS_GPIO_23_16_SOFT_RESET |
| 1 | MSS_GPIO_15_8_SYSRESET_SEL | 0 | 0: Selects the combination of either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric to reset the GPIO 1: Causes GPIO[15:8] to be held in reset by the soft reset signal MSS_GPIO_15_8_SOFT_RESET |
| 0 | MSS_GPIO_7_0_SYSRESET_SEL | 0 | 0: Selects the combination of either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric to reset the GPIO 1: Causes GPIO[7:0] to be held in reset by the soft reset signal MSS_GPIO_7_0_SOFT_RESET |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.