| [31:8] | Reserved | 0 | — |
| 7 | USER_M3_RESET_DETECT | 0x1 | Indicates that an M3 user reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. Reset signal: FAB_M3_RESET_M3_CLK_N. |
| 6 | USER_RESET_DETECT | 0x1 | Indicates that a MSS user reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. Reset signal: MSS_RESET_N_F2M. |
| 5 | WDOG_RESET_DETECT | 0x1 | Indicates that a Watchdog reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. Reset signal: WDOGTIMEOUT_M3_CLK_N. |
| 4 | LOCKUP_RESET_DETECT | 0x1 | Indicates that a Cortex-M3 processor lockup reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. The reset signal for this bit is LOCKUP_DEL2_N. |
| 3 | SOFT_RESET_DETECT | 0x1 | Indicates that a soft reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. The reset signal for this bit is SYSRESETREQ_DEL2_N. |
| 2 | CONTROLLER_M3_RESET_DETECT | 0x1 | Indicates that a controller M3 reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. The reset signal for this bit is M3_RESET_M3_CLK_N. |
| 1 | CONTROLLER_RESET_DETECT | 0x1 | Indicates that an MSS controller reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. Reset signal: SC_MSS_RESET_M3_CLK_N. |
| 0 | PO_RESET_DETECT | 0x1 | Indicates that a power-up reset has occurred. During the device boot sequence, this register should be cleared to Arm it to detect the next reset event. The reset signal for this bit is PO_RESET_M3_CLK_N. |
