21.5.25 MDDR Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:4] | Reserved | 0 | |
| 3 | PHY_SELF_REF_EN | 0 | Indicates that the DRAM has been put into self-refresh. This is used for automatic locking of the codes during intermediate runs for DDRC. Not used in non-DDRIO modes. |
| 2 | F_AXI_AHB_MODE | 0 | Used by the SMC_FIC, DDR_FIC, and DDR CTL to select the AXI/AHB interface in the fabric. Allowed values: 0: AHB interface is selected 1: AXI interface is selected |
| 1 | SDR_MODE | 0 | Used to select whether the MSS AXI interface accesses DDR memory or SDR memory (or other memory types) inside the fabric. Allowed values: 0: DDR memory is selected 1: SDR memory or other memory type is selected |
| 0 | MDDR_CONFIG_LOCAL | 0x1 | Configures whether the MSS AHBTOAPB2 bridge can directly access the APB slave within the MDDR subsystem or whether the APB slave is connected to the fabric. Allowed values: 0: AHBTOAPB2 bridge cannot access MDDR APB slave 1: AHBTOAPB2 bridge can access MDDR APB slave Reset signal for this bit is CC_RESET_N. |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.