21.5.38 MSS DDR Fabric Alignment Clock Controller (FACC) Configuration Register 1

Table 21-45. MSSDDR_FACC1_CR
Bit Number	Name	Reset Value	Description
[31:28]	Reserved	0	—
27	FACC_FAB_REF_SEL	0	Selects the source of the reference clock to be supplied to the MPLL. Allowed values: 0: 50 MHz RC 1: Fabric clock (CLK_BASE)
26	CONTROLLER_PLL_INIT	0x1	Indicates whether the FACC is to be configured for PLL initialization mode. The user can write to it when it detects that the MPLL has lost lock and it wants to switch to a known good clock source until the MPLL comes back into lock. This causes the 50 MHz clock to be selected through to the MSS. It also interrupts the System Controller, which then waits for the MPLL to come into lock before clearing this bit and thereby selecting the MPLL output as the MSS clock source again. The allowed values of this bit are: 0: The corresponding FACC multiplexer select lines or clock gate control line co mes from the normal run-time configuration signals (from relevant MSS system register bits). 1: The corresponding FACC multiplexer select lines or clock gate control line are overridden by hardwired PLL initialization selection, as described below: – Override the four no-glitch multiplexers related to the aligned clocks, so that they select CLK_STANDBY as the source of M3_CLK, APB_0_CLK, APB_0_CLK and DDR_SMC_FIC_CLK. – Override the selection of the FACC standby multiplexer, so that it selects the RCOSC_25_50MHZ clock as the source of CLK_STANDBY. – Override the selection of the FACC reference multiplexer, so that it selects CLK_BASE clock as the source of MPLL_REF_CLK. – Override the value of the PLL bypass configuration signal, so that it forces the MPLL bypass path not to be used. – Force MDDR_CLK to be gated off.
25	PERSIST_CC	0	Feeds into the MSS Reset Controller. Based on the value of PERSIST_CC, the Reset Controller asserts a reset (CC_RESET_N) to the FACC (which inverts it and passes it on to the PLL as MSSDDR_PLL_RESET), either on every MSS system reset or just on power-up reset. This field is to be configured using flash bits. Do not write to this field. The only allowable value for this bit is 1. The reset signal for this register is PORESET_N.
[21:19]	DDR_FIC_DIVISOR	0	Indicates the ratio between CLK_A and DDR_SMC_FIC_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are listed in Table 21-46.
[18:16]	FIC_1_DIVISOR	0	Indicates the ratio between CLK_A and the clock being used in the fabric, to clock the soft IP block which is interfacing to FIC_1 of the MSS. The user can write to this field dynamically during run time, even when the source clock is active. The allowed ratios for CLK_A:fabric clock (FIC_1) is listed in Table 21-46.
[15:13]	FIC_0_DIVISOR	0	Indicates the ratio between CLK_A and the clock being used in the fabric, to clock the soft IP block which is interfacing to FIC_0 of the MSS. The user can write to this field dynamically during run time, even when the source clock is active. The allowed ratios for CLK_A:fabric clock (FIC_0) are listed in Table 21-46.
12	FACC_GLMUX_SEL	0	Contains the select line for the four no-glitch multiplexers within the FACC, which are related to the aligned clocks. All four of these multiplexers are switched by one signal. Allowed values: 1: M3_CLK, APB_0_CLK, APB_1_CLK, DDR_SMC_FIC_CLK all driven from CLK_STANDBY 0: M3_CLK, APB_0_CLK, APB_1_CLK, DDR_SMC_FIC_CLK all driven from stage B dividers Configure this field using flash bits. Do not write to this field.
[11:9]	M3_CLK_DIVISOR	0	Indicates the ratio between CLK_A and M3_CLK. The user can write to this field dynamically during run time, even when the source clock is active.
8	DDR_CLK_EN	0	Determines whether or not the clock to the MDDR block is to be gated off. Allowed values: 0: MDDR_CLK is gated off 1: MDDR_CLK is allowed to propagate through to MDDR block Do not write to this field dynamically while the source clock is active.
[7:5]	APB1_DIVISOR	0	Indicates the ratio between CLK_A and APB_1_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are described in Table 21-46.
[4:2]	APB0_DIVISOR	0	Indicates the ratio between CLK_A and APB_0_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are described in Table 21-46.
[1:0]	DIVISOR_A	0	Indicates the ratio between CLK_SRC and CLK_A. Allowed values: 00: 1:1 01: 2:1 10: 3:1 11: Reserved Configure this field statically. Do not write to this field while the source clock is active.

[31:28]

Reserved

0

—

27

FACC_FAB_REF_SEL

0

Selects the source of the reference clock to be supplied to the MPLL. Allowed values:

0: 50 MHz RC

1: Fabric clock (CLK_BASE)

26

CONTROLLER_PLL_INIT

0x1

Indicates whether the FACC is to be configured for PLL initialization mode. The user can write to it when it detects that the MPLL has lost lock and it wants to switch to a known good clock source until the MPLL comes back into lock. This causes the 50 MHz clock to be selected through to the MSS. It also interrupts the System Controller, which then waits for the MPLL to come into lock before clearing this bit and thereby selecting the MPLL output as the MSS clock source again. The allowed values of this bit are:

0: The corresponding FACC multiplexer select lines or clock gate control line co mes from the normal run-time configuration signals (from relevant MSS system register bits).

1: The corresponding FACC multiplexer select lines or clock gate control line are overridden by hardwired PLL initialization selection, as described below:

– Override the four no-glitch multiplexers related to the aligned clocks, so that they select CLK_STANDBY as the source of M3_CLK, APB_0_CLK, APB_0_CLK and DDR_SMC_FIC_CLK.

– Override the selection of the FACC standby multiplexer, so that it selects the RCOSC_25_50MHZ clock as the source of CLK_STANDBY.

– Override the selection of the FACC reference multiplexer, so that it selects CLK_BASE clock as the source of MPLL_REF_CLK.

– Override the value of the PLL bypass configuration signal, so that it forces the MPLL bypass path not to be used.

– Force MDDR_CLK to be gated off.

25

PERSIST_CC

0

Feeds into the MSS Reset Controller. Based on the value of PERSIST_CC, the Reset Controller asserts a reset (CC_RESET_N) to the FACC (which inverts it and passes it on to the PLL as MSSDDR_PLL_RESET), either on every MSS system reset or just on power-up reset.

This field is to be configured using flash bits. Do not write to this field. The only allowable value for this bit is 1. The reset signal for this register is PORESET_N.

[21:19]

DDR_FIC_DIVISOR

0

Indicates the ratio between CLK_A and DDR_SMC_FIC_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are listed in Table 21-46.

[18:16]

FIC_1_DIVISOR

0

Indicates the ratio between CLK_A and the clock being used in the fabric, to clock the soft IP block which is interfacing to FIC_1 of the MSS. The user can write to this field dynamically during run time, even when the source clock is active. The allowed ratios for CLK_A:fabric clock (FIC_1) is listed in Table 21-46.

[15:13]

FIC_0_DIVISOR

0

Indicates the ratio between CLK_A and the clock being used in the fabric, to clock the soft IP block which is interfacing to FIC_0 of the MSS. The user can write to this field dynamically during run time, even when the source clock is active. The allowed ratios for CLK_A:fabric clock (FIC_0) are listed in Table 21-46.

12

FACC_GLMUX_SEL

0

Contains the select line for the four no-glitch multiplexers within the FACC, which are related to the aligned clocks. All four of these multiplexers are switched by one signal. Allowed values:

1: M3_CLK, APB_0_CLK, APB_1_CLK, DDR_SMC_FIC_CLK all driven from CLK_STANDBY

0: M3_CLK, APB_0_CLK, APB_1_CLK, DDR_SMC_FIC_CLK all driven from stage B dividers

Configure this field using flash bits. Do not write to this field.

[11:9]

M3_CLK_DIVISOR

0

Indicates the ratio between CLK_A and M3_CLK. The user can write to this field dynamically during run time, even when the source clock is active.

8

DDR_CLK_EN

0

Determines whether or not the clock to the MDDR block is to be gated off. Allowed values:

0: MDDR_CLK is gated off

1: MDDR_CLK is allowed to propagate through to MDDR block

Do not write to this field dynamically while the source clock is active.

[7:5]

APB1_DIVISOR

0

Indicates the ratio between CLK_A and APB_1_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are described in Table 21-46.

[4:2]

APB0_DIVISOR

0

Indicates the ratio between CLK_A and APB_0_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are described in Table 21-46.

[1:0]

DIVISOR_A

0

Indicates the ratio between CLK_SRC and CLK_A. Allowed values:

00: 1:1

01: 2:1

10: 3:1

11: Reserved

Configure this field statically. Do not write to this field while the source clock is active.