Gated Auto-Shutdown Mode

For some types of power control applications, it is useful to delay the effect of the auto-shutdown input. The ASDGM control bit (CCPxCON2[14]) enables gated shutdown operation. When ASDGM is set, the effect of an auto-shutdown signal input does not take place until the next PWM period boundary. This allows the PWM generator to produce the entire pulse that was programmed for the present cycle.

Pulses are terminated by the hardware beginning on the next cycle. Pulses will resume on the next PWM period after the shutdown event has ended.

Note: Pulses only resume automatically if PWMRSEN = 1. If PWMRSEN = 0, the ASEVT status bit must be cleared in software for pulses to resume.

The Gated mode allows the Automatic Shutdown mode to be used along with a comparator to implement a ‘Pulse Skipping’ or ‘Gated Oscillator’ Switch mode power supply. The inductor is charged for a fixed period of time with each pulse, putting a specific amount of energy into the supply. If the output voltage (current) is high enough, then the comparator gates the pulses.

Figure 27-23. Gated Auto-Shutdown Mode
Note:
  1. Any device-defined hardware shutdown event when the corresponding ASDGx bit is set or when the SSDG bit is set.
Note:
  1. If automatic restarts are not enabled, the application may also need to clear the ASEVT bit.
  2. Any enabled shutdown source selected by the ASDGx bits and the SSDG software shutdown bit takes priority over a software write to the ASEVT bit. The Fault condition cannot be exited unless all shutdown sources are inactive.