10.4.10.2 Axcelerator® RAM I/O Description
The following table lists the I/O description of a Axcelerator RAMs.
| Name | Type | Required/Optional | Description |
|---|---|---|---|
| Data | IN | Required | Write Data Port |
| WAddress | IN | Required | Write Address Bus |
| WE | IN | Optional | Write Enable |
| WClock | IN | Required | Write Clock |
| Q | OUT | Required | Read Data Port |
| RAddress | IN | Required | Read Address Bus |
| RE | IN | Optional | Read Enable |
| RClock | IN | Required | Read Clock |