10.4.10.1 Axcelerator® RAM Functionality
Axcelerator provides dedicated blocks of RAM. Each block has a read port and a write port. Both ports are configurable to any size from 4Kx1 to 128x36; thereby, allowing built-in bus width conversion (see following table). Each port is completely independent and fully synchronous.
| Width | Depth | ADDR Bus | Data Bus |
|---|---|---|---|
| 1 | 4096 | ADDR [11:0] | DATA [0] |
| 2 | 2048 | ADDR [10:0] | DATA [1:0] |
| 4 | 1024 | ADDR[9:0] | DATA[3:0] |
| 9 | 512 | ADDR[8:0] | DATA[8:0] |
| 18 | 256 | ADDR[7:0] | DATA[17:0] |
| 36 | 128 | ADDR[6:0] | DATA[35:0] |