10.4.5.3.1 Data is Valid for Only a Single Clock After a Read Operation

The behavior of the depth cascaded FIFO is not the typical behavior of FIFOs. After a read is asserted and the data is made available at the data bus of the FIFO, the data is valid for only a single clock cycle. The cause is the depth cascade uses a ping-pong architecture and a read operation advances the enable to the next FIFO block. Thus, the next FIFO block’s data becomes available after a single clock cycle.

This behavior does not appear in pre-synthesis simulations. Only after post-synthesis or post-layout simulations, where timing delays are included, does the issue become visible.

Figure 10-59. Basic Single and Multiple Read of Depth Cascaded FIFO
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If the client logic requires the data to remain available on the data out port, the following workaround is available:

Figure 10-60. FIFO Read Data Workaround
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An extra data stage pipeline is added right after the FIFO with a delayed read signal as an enable. The previous diagram is for the FIFO that does not use the pipeline feature, if the pipeline on the FIFO is enabled then an extra stage of delay for the read signal is required.