1.2.1 Analog System Builder Reference
The Analog System Builder (ASB) uses some terminologies that may be unfamiliar. The following table lists terms and acronyms that appear in the software and the help.
| Term | Description |
|---|---|
| ADC | Analog-to-digital converter |
| ASSC | Analog sample sequence controller; sets the sample order in the ADC (includes IP + RAM) |
| Analog System | The complete system, including the analog block (AB) hard IP and one or more of ASSC, SMEV, and SMTR soft IPs. |
| SMEV | Evaluates the converted analog data (IP + RAM) |
| SMTR | Processes the evaluated analog data and generates flag signals on certain conditions (includes IP + RAM) |
| AB | Analog block - The hard macro in the CAE library that includes the analog MUX and the ADC |
| Analog MUX | The 32 -1 MUX, select signals of which determine the channel being sampled by the analog to digital converter. |
| ACM | Analog Configuration MUX - stores configuration data related to analog channels (channel type, pre-scalar value, polarity, etc.) |
| FMSB | Flash Memory System Builder |
| INIT IP | INIT / CFG Soft IP, responsible for all initialization and Save activity to the NVM |
| ASB | Analog System Block. Analog System top level, includes the Analog Block (AB) and Analog System Soft IP. |
| FMB | Flash memory block. Flash Memory top level, includes Flash Memory System Builder and INIT IP. |
| FASTCLK | Intended clock during normal system execution |
| SLOWCLK | Intended clock during system initialization |