1.2.10 Analog System Builder Calibration Output Files

The ASB Calibration output files are placed in the common folder.

HDL Source Files (in <workspace_directory/<common>/vhdl or /verilog directory)

calibip.vhd/.v
calibip_brentkung_24.vhd/.v
calibip_clram.vhd/.v
capibip_compute_block.vhd/.v
calibip_ram512x9_afs.vhd/.v
calibip_ripple_24.vhd/.v
/smartgen/<corename>/<corename>_calibip_wrapper.v - Top level HDL wrapper for CalibIP

<corename>_calibcoefficient.mem - Contains Flash Memory System Builder content for the M (GAIN) and C (OFFSET) coefficient section of Flash Memory System Builder.
This is imported by Flash Memory Builder to generate the Simulation Memory File. It is required to allow simulation to work properly, the M and C data in this file are populated with M=1 and C=0. Since the AB simulation model provides ‘ideal’ conversion results, no calibration is needed so populating the coefficient data with 1 and 0 emulates that scenario.
<corename>_calibip_wrapper.hex - Contains Flash Memory System Builder content for the CalibROM section of the Flash Memory System in IntelHex format.
<corename>_calibip_wrapper_R0C0.mem -Contains Flash Memory System Builder content for the CalibROM section of the Flash Memory System in binary format.
<corename>_calibrom.mem - Contains Flash Memory System Builder content for the CalibROM section of the Flash Memory System in the correct memory format. This is imported by the Flash Memory System Builder to generate the Simulation and Programming Memory File.