1.2.2 ASB Port List

All signals are active high unless explicitly specified.


Name	Type	Description
SYS_CLK	INPUT	Clock input for Analog Block and Soft IP
SYS_RESET	INPUT	Active low asynchronous reset
VAREF	INOUT	Voltage reference; connects to external voltage for external voltage reference.Returns the internal VREF in the case of internal voltage reference. Must be connected to a top-level port without any I/Os.
Analog Input Channels	INPUT	User specified or port names. Analog input channels being used.
Analog Output Channels	OUTPUT	User specified port names; analog output channels being used.
Input Channel Compare Flags	OUTPUT	Threshold flags specified for each peripheral
Flash Memory Block Interface
INIT_DATA[8:0]	INPUT	Initialization data
INIT_DONE	INPUT	Initialization done signal from the Flash Memory Block
INIT_ACM_WEN	INPUT	Initialization ACM write enable
INIT_ASSC_WEN	INPUT	Initialization ASSC RAM write enable
INIT_EV_WEN	INPUT	Initialization SMEV RAM write enable
INIT_TR_WEN	INPUT	Initialization SMTR RAM write enable
INIT_ACM_RTC_WEN	INPUT	Initialization of ACM during second pass; only exported when you use the RTC Peripheral.
Status Signals
DATAVALID	OUPUT	Indicates data from the ADC is valid
ASSC_DONE	OUTPUT	Indicates the ASSC is finished processing the current sampling slot
ASSC_WAIT	OUTPUT	Indicates the ASSC is inserting wait states to accommodate SMEV and SMTR processing times.
ASSC_CHSAT	OUTPUT	Sampled channel saturated; indicates that the current channel sampled by the ADC has a value that is saturated (too high for the ADC voltage range). Once this output becomes active, it remains active until the next timeslot is processed. If this output is active, you may need to move up to a higher voltage range (decrease prescaler value for the particular analog input pad).
ASSC_CHLATD	OUTPUT	Channel selector latched; signal indicates that the ADC_CHNR[4:0] (ADC channel selector) value has been latched.