10.4.4.2.2 Area and Speed in the Soft FIFO Controller

The size and operating frequency of the Soft FIFO design is dependent upon the configuration and optional features that are enabled.

Note: Consider the following notes about area and speed:
  • A single clock design is smaller and faster because the synchronizers and gray encoder/decoders are not required.
  • Gray encoders/decoders are generally required (or strongly recommended) in dual-clock designs, especially for things like asynchronous FIFOs. They are not typically needed in single-clock designs.
  • Port depths that are not a power of 2 generate a larger and slower design. The reason is that logic optimization occurs for power-of-2 depths. Thus, if you need a 66 x 8 FIFO, it may be more advantageous to select a FIFO depth of 64 or 128 if area and/or speed are concerns.

Gray encoder

Gray encoders are used in the embedded FIFO controller to improve reliability in clock-domain crossing scenarios. The device datasheet (DS) describes this behavior as follows:
  • Each memory block contains its own embedded FIFO controller.
  • Each FIFO supports one read port and one write port.
The embedded FIFO controller consumes no internal FPGA logic and provides:
  • Glitch-free FIFO status flags
  • Gray-code address counters and pointers to prevent metastability
  • Overflow and underflow protection.

In the FIFO implementation, Gray code counters are used for the read and write address pointers, as well as for the generation of FIFO status flags (such as full and empty). Because only a single bit changes between consecutive Gray code values, the risk of metastability is greatly reduced when pointer values are transferred between the read and write clock domains. This ensures stable and glitch-free flag generation even when the FIFO operates asynchronously.