21.9.11 Specifying Clock Source Latency

Use clock source latency to specify the delay from the clock generation point to the clock definition point in the design.

Clock source latency defines the delay between an external clock source and the definition pin of a clock within SmartTime. It behaves much like an input delay constraint.

You can specify both an "early" delay and a "late" delay for this latency, providing an uncertainty which SmartTime propagates through its calculations. Rising and falling edges of the same clock can have different latencies. If only one value is provided for the clock source latency, it is taken as the exact latency value, for both rising and falling edges.

To specify the clock source latency:

Add the constraint in the editable constraints grid or open the Set Clock Source Latency dialog box using one of the following methods:
- From the SmartTime Actions menu, choose Constraints > Clock Source Latency.
- Click the icon.
- Right-click Clock Source Latency in the Constraint Browser.
- Double-click any field in the Clock Source Latency grid.
Select a clock pin on which to set the source latency. You can only specify a clock source latency on a clock pin that has a clock constraint. Additionally, you may apply only one clock source latency constraint to each constrained clock pin.
Enter the Late Rise, Early Rise, Late Fall and Early Fall values as required for your design.

Note: An ‘early’ value larger than a ‘late’ value can result in optimistic timing analysis.
Select the Falling Same As Rising check box to indicate that falling clock edges have the same latency as rising clock edges.
Select the Early Same As Late check box to use a single value for the clock latency, rather than a range, by clicking the checkbox.
Enter any comments to be attached to the constraint.
Click OK. The new constraint appears in the constraints list.

Note: When you choose Commit from the File menu, SmartTime saves the newly-created constraint in the database.