10.4.12.3 Dual Port RAM for IGLOO®, ProASIC® 3 and Fusion Parameter Description
The following table describes all the parameters of the Dual Port RAM signals in generated netlists.
| Name | Type | Genfile Parameter | Bit/Bus | Description |
|---|---|---|---|---|
| ADDRA | IN | ADDRESSA_PN | BUS | Address for port A |
| DINA | IN | DATAA_IN_PIN | BUS | Data in for Port A |
| BLKA | IN | BLKA_PN | Bit | Block enable for Port A |
| RWA | IN | RWA_PN | Bit | Signal to switch between Read and Write modes; Low = Write, High = Read |
| CLKA | IN | CLKA_PN | Bit | Clock for Port A |
| ADDRB | IN | ADDRESSB_PN | Bus | Address for Port B |
| DINB | IN | DATAB_IN_PN | Bus | Data in for Port B |
| BLKB | IN | BLKB_PN | Bit | Block enable for Port B |
| RWB | IN | RWB_PN | Bus | Signal to switch between Read and Write modes; Low = Write, High = Read |
| CLKB | IN | CLKB_PN | Bit | Clock for Port B |
| CLKAB | IN | CLOCK_PN | Bit | Clock for single clock |
| DOUTA | OUT | DATAA_OUT_PN | Bus | Data output for Port A |
| DOUTB | OUT | DATAB_OUT_PN | Bus | Data output for Port B |
| LP | IN | LP_PN | Bit | Low power input pin |
| FF | IN | FF_PN | Bit | Flash*Freeze input pin |
| RESET | RESET | Asynchronous reset |