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10
SmartGen Cores Reference
10.4
Memory and Controllers
10.4.3
Axcelerator FIFO
10.4.3.4
Axcelerator FIFO Implementation Rules
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SmartGen Cores Reference
10.1
Basic Blocks
10.2
Clock and Management
10.3
Fusion Peripherals
10.4
Memory and Controllers
10.4.1
Creating a RAM for IGLOO®, ProASIC® 3, SmartFusion® and Fusion
10.4.2
FIFO Flag Controller (no RAM)
10.4.3
Axcelerator FIFO
10.4.3.1
Axcelerator FIFO Functionality
10.4.3.2
Axcelerator FIFO I/O Description
10.4.3.3
Axcelerator FIFO Parameter Description
10.4.3.4
Axcelerator FIFO Implementation Rules
10.4.3.4.1
FIFO Flag Usage
10.4.4
Soft FIFO Controller
10.4.5
Synchronous/Asynchronous Dual Port FIFO for ProASIC® and ProASIC®PLUS
10.4.6
Synchronous Dual Port FIFO with Flags
10.4.7
Synchronous Dual Port FIFO without Flags
10.4.8
Synchronous FIFO for IGLOO®, ProASIC® 3, SmartFusion® and Fusion®
10.4.9
FIFO Using Distributed Memory for ProASICPLUS®
10.4.10
Axcelerator® RAM
10.4.11
RAM Content Manager Summary
10.4.12
Dual Port RAM for IGLOO®, ProASIC® 3 and Fusion®
10.4.13
Synchronous/Asynchronous Dual Port RAM for DX/MX
10.4.14
Synchronous/Asynchronous Dual Port RAM for ProASICPLUS®
10.4.15
Two Port RAM
10.4.16
RAM with Initialization
10.5
Power Management
10.6
Revision History
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Microchip FPGA Support
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Microchip Information
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HDL Coding Style
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Antifuse Macro Library Guide for Software
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MultiView Navigator
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IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
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ProASIC and ProASIC PLUS Macro Library for Software
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PinEditor (non-MVN)
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SmartPower
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SmartTime
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Timer
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VHDL Vital Simulation
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Verilog Simulation
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About Microchip
10.4.3.4 Axcelerator FIFO Implementation Rules
Rev: A
