22.6.4 CCPx Control 2 High Register

Name:	CCPxCON2H
Offset:	0x956, 0x976, 0x99E, 0x9C2, 0x9E6, 0xA0A, 0xA2E, 0xA52, 0xA76


Bit	15	14	13	12	11	10	9	8
	OENSYNC							OCAEN
Access	R/W							R/W
Reset	0							0


Bit	7	6	5	4	3	2	1	0
	ICGSM[1:0]			AUXOUT[1:0]		ICS[2:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0

Bit 15 – OENSYNC Output Enable Synchronization bit

Value	Description
`1`	Update by output enable bits occurs on the next Time Base Reset or rollover
`0`	Update by output enable bits occurs immediately

Bit 8 – OCAEN Output Enable/Steering Control bit

Value	Description
`1`	OCx pin is controlled by the CCPx module and produces an output compare or PWM signal
`0`	OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin

Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits

Value	Description
`11`	Reserved
`10`	One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = `1`)
`01`	One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = `0`)
`00`	Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will disable future capture events

Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits

Value	Description
`11`	Input capture or output compare event; no signal in Timer mode
`10`	Signal output is defined by module operating mode (see Auxiliary Output)
`01`	Time base rollover event (all modes)
`00`	Disabled

Bits 2:0 – ICS[2:0] Input Capture Source Select bits

Value	Description
`111`	CLC4 Output
`110`	CLC3 Output
`101`	CLC2 Output
`100`	CLC1 Output
`011`	Comparator 3
`010`	Comparator 2
`001`	Comparator 1
`000`	SCCP Input Capture x (ICx) pin (PPS)