22.6.3 CCPx Control 2 Low Register

Name: CCPxCON2L
Offset: 0x954, 0x974, 0x99C, 0x9C0, 0x9E4, 0xA08, 0xA2C, 0xA50, 0xA74

Bit 15141312111098 
 PWMRSENASDGM SSDG     
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
 ASDG[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 15 – PWMRSEN CCPx PWM Restart Enable bit

ValueDescription
1

ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended

0

ASEVT bit must be cleared in software to resume PWM activity on output pins

Bit 14 – ASDGM CCPx Auto-Shutdown Gate Mode Enable bit

ValueDescription
1

Waits until the next Time Base Reset or rollover for shutdown to occur

0

Shutdown event occurs immediately

Bit 12 – SSDG CCPx Software Shutdown/Gate Control bit

ValueDescription
1

Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM bit still applies)

0

Normal module operation

Bits 7:0 – ASDG[7:0] CCPx Auto-Shutdown/Gating Source Enable bits

ValueDescription
1

ASDGx Source n is enabled (see Auto-Shutdown and Gating Sources for auto-shutdown/gating sources)

0

ASDGx Source n is disabled