22.6.6 CCPx Status Register

Legend: C = Clearable bit; W1 = Write ‘1’ Only bit

Name: CCPxSTATL
Offset: 0x95C, 0x980, 0x9A4, 0x9C8, 0x9EC, 0xA10, 0xA34, 0xA58, 0xA7C

Bit 15141312111098 
      ICGARM   
Access R 
Reset 0 
Bit 76543210 
 CCPTRIGTRSETTRCLRASEVTSCEVTICDISICOVICBNE 
Access RW1W1R/CR/CR/CR/CR/C 
Reset 00000000 

Bit 10 – ICGARM Input Capture Gate Arm bit

ValueDescription
1

Input capture gating logic is armed for a one-shot gate event when ICGSM[1:0] = 01 or 10; bit always reads as ‘0’
0

Input capture gating logic is not armed for a one-shot gate event when ICGSM[1:0] = 01 or 10; bit always reads as ‘0’

Bit 7 – CCPTRIG CCPx Trigger Status bit

ValueDescription
1

Timer has been triggered and is running
0

Timer has not been triggered and is held in Reset

Bit 6 – TRSET CCPx Trigger Set Request bit

Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).

Bit 5 – TRCLR CCPx Trigger Clear Request bit

Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).

Bit 4 – ASEVT CCPx Auto-Shutdown Event Status/Control bit

ValueDescription
1

A shutdown event is in progress; CCPx outputs are in the Shutdown state
0

CCPx outputs operate normally

Bit 3 – SCEVT Single Edge Compare Event Status bit

ValueDescription
1

A single edge compare event has occurred
0

A single edge compare event has not occurred

Bit 2 – ICDIS Input Capture x Disable bit

ValueDescription
1

Event on Input Capture x pin (ICx) does not generate a capture event
0

Event on Input Capture x pin will generate a capture event

Bit 1 – ICOV Input Capture x Buffer Overflow Status bit

ValueDescription
1

The Input Capture x FIFO buffer has overflowed
0

The Input Capture x FIFO buffer has not overflowed

Bit 0 – ICBNE Input Capture x Buffer Status bit

ValueDescription
1

Input Capture x buffer has data available
0

Input Capture x buffer is empty