22.6.5 CCPx Control 3 High Register

Name: CCPxCON3H
Offset: 0x95A, 0x97E, 0x9A2, 0x9C6, 0x9EA, 0xA0E, 0xA32, 0xA56, 0xA74

Bit 15141312111098 
 OETRIGOSCNT[2:0]     
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
   POLACE PSSACE[1:0]PSSBDF[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 15 – OETRIG CCPx Dead-Time Select bit

ValueDescription
1

For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0

Normal output pin operation

Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits

ValueDescription
111

Extends one-shot event by 7 time base periods (8 time base periods total)
110

Extends one-shot event by 6 time base periods (7 time base periods total)
101

Extends one-shot event by 5 time base periods (6 time base periods total)
100

Extends one-shot event by 4 time base periods (5 time base periods total)
011

Extends one-shot event by 3 time base periods (4 time base periods total)
010

Extends one-shot event by 2 time base periods (3 time base periods total)
001

Extends one-shot event by 1 time base period (2 time base periods total)
000

Does not extend one-shot trigger event

Bit 5 – POLACE CCPx Output Pins, OCxA, OCxC and OCxE, Polarity Control bit

ValueDescription
1

Output pin polarity is active-low
0

Output pin polarity is active-high

Bits 3:2 – PSSACE[1:0] PWMx Output Pins, OCxA, OCxC and OCxE, Shutdown State Control bits

ValueDescription
11

Pins are driven active when a shutdown event occurs
10

Pins are driven inactive when a shutdown event occurs
0x

Pins are in a High-Impedance state when a shutdown event occurs

Bits 1:0 – PSSBDF[1:0]  PWMx Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits

ValueDescription
11

Pins are driven active when a shutdown event occurs
10

Pins are driven inactive when a shutdown event occurs
0x

Pins are in a High-Impedance state when a shutdown event occurs