11.5.18 Inactivity Watchdog Timeout (High)
| Name: | IWDTOH |
| Address: | 0x003E |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TIMEOUT[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TIMEOUT[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | |
Bits 15:0 – TIMEOUT[31:16] Inactivity Watchdog Timeout
This field configures the upper 16 bits of the 32-bit integrated PHY/MAC MII and PHY register access
inactivity watchdog timeout in increments of 200 ns.
Note: The default value of 0x00989680
results in a timeout of 2 seconds.