11.5.6 Interrupt Mask 2 Register

Name: IMSK2
Address: 0x001D

Bit 15141312111098 
 WKEMDIMWKEWIMUV33M 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11110001 
Bit 76543210 
 OTMIWDTOM 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bit 10 – WKEMDIM MDI Wakeup Interrupt Mask

When clear, this bit will enable assertion of the PHY Interrupt status (PHYINT) in the OPEN Alliance Status 0 (OA_STATUS0) register when the MDI Wake-up (WKEMDI) status bit is set.
ValueDescription
0 MDI wake-up interrupt enabled
1 MDI wake-up interrupt disabled

Bit 9 – WKEWIM WAKE_IN Wake-up Interrupt Mask

When clear, this bit will enable assertion of the PHY Interrupt status (PHYINT) in the OPEN Alliance Status 0 (OA_STATUS0) register when the WAKE_IN Wake-up (WKEWI) status bit is set.
ValueDescription
0 WAKE_IN wake-up interrupt enabled
1 WAKE_IN wake-up interrupt disabled

Bit 8 – UV33M 3.3V supply Under-Voltage Interrupt Mask

When clear, this bit will enable assertion of the PHY Interrupt status (PHYINT) in the OPEN Alliance Status 0 (OA_STATUS0) register when the 3.3V supply Under-Voltage (UV33) status bit is set.
ValueDescription
0 3.3V supply under-voltage interrupt enabled
1 1.8V supply under-voltage interrupt disabled

Bit 6 – OTM Over-Temperature Error Interrupt Mask

When clear, this bit will enable assertion of the PHY Interrupt status (PHYINT) in the OPEN Alliance Status 0 (OA_STATUS0) register when the Over-Temperature Error (OT) status bit is set.
ValueDescription
0 Over-temperature error interrupt enabled
1 Over-temperature error interrupt disabled

Bit 5 – IWDTOM Inactivity Watchdog Timeout Interrupt Mask

When clear, this bit will enable assertion of the PHY Interrupt status (PHYINT) in the OPEN Alliance Status 0 (OA_STATUS0) register when the Inactivity Watchdog Timeout (IWDTO) status bit is set.
ValueDescription
0 Inactivity watchdog timeout interrupt enabled
1 Inactivity watchdog timeout interrupt disabled