31.6.17 CRC Polynomial REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CRCPOLY |
| Offset: | 0x40 |
| Reset: | 0x00000001 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CRCPOLY[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CRCPOLY[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCPOLY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCPOLY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 31:0 – CRCPOLY[31:0] When CRCMODE.PLEN32==0: CRCPOLY[31:16] is don't care. CRCPOLY[15:0] is the polynomial coefficients. CRCPOLY[0] and CRCPOLY[16] are implied and are always 1. When CRCMODE.PLEN32==1: CRCPOLY[31:0] is the polynomial coefficients. CRCPOLY[0] and CRCPOLY[32] are implied and are always 1.
When CRCMODE.PLEN32=0: CRCPOLY[31:16] is don’t care. CRCPOLY[15:0] is the polynomial coefficients.
CRCPOLY[0] and CRCPOLY[16] are implied and are always 1.
When CRCMODE.PLEN32=1: CRCPOLY[31:0] is the polynomial coefficients.
CRCPOLY[0] and CRCPOLY[32] are implied and are always 1.
| Value | Name | Description |
|---|---|---|
| 1 | Enable the XOR input to the shift register at the associated bit position | |
| 0 | Disable the XOR input to the shift register at the associated bit position |