31.6.1 CTRL A REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0 |
| Reset: | 0x00008000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ARB | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RDBUFWS[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AUTOWS | ADRWS | FWS[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRIV | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 24 – ARB AHB Arbitration scheme
| Value | Name | Description |
|---|---|---|
| 1 | FIXED | Fixed priority AHB0 highest to AHB<FCR_AHB_PORTS_NB-1> lowest |
| 0 | ROUNDROBIN | Round Robin Arbitration |
Bits 19:16 – RDBUFWS[3:0] Read Buffer deterministic access requires AUTOWS=0.
When returning data from the AHB read buffer, insert wait states to match ADRWS and FWS from Flash based on RDBUFWS.
| Value | Name | Description |
|---|---|---|
| 1 | DETERMINISTIC | ADRWS + FWS wait state for hits to AHB read buffer |
| 0 | ZEROWS | 0 Wait States |
Bit 15 – AUTOWS Taws = Tacc + 5ns + 2 clocks
Taws = Tacc + 5ns + 2 clocks
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | Use Automatic wait states: Total flash wait states are ADRWS + Taws |
| 0 | DISABLE | Use FWS: Total flash wait states are ADRWS + FWS |
Bit 14 – ADRWS For Total flash wait states see AUTOWS.
For Total flash wait states see AUTOWS.
| Value | Name | Description |
|---|---|---|
| 1 | ONE | Add 1 Address Wait State - allowing for higher clock frequencies |
| 0 | ZERO | Add 0 Address Wait States - allowing for higher performance at lower clock frequencies |
Bits 11:8 – FWS[3:0] For Total flash wait states see AUTOWS. ... Note: This is not the wait states seen by the CPU.
1111= Fifteen Wait States
1110= Fourteen Wait States
...
0001= One Wait State
0000= Zero Wait States
Note: This is not the wait states
seen by the CPU. For Total Flash wait states see AUTOWS.
| Value | Name | Description |
|---|---|---|
| 15 | Fifteen Wait States | |
| 14 | Fourteen Wait States | |
| 1 | One Wait State | |
| 0 | Zero Wait States |
Bit 2 – PRIV Privileged Access Only
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | Macro registers only accessible in privileged accesses |
| 0 | DISABLE | Macro register accessible in privileged and unprivileged accesses. |