31.6.2 CTRL B REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x4 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PREFDIS | CHEDIS | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SLP[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHEINV | TEMP | PRM | |||||||
| Access | R/S/HC | R/S/HC | R/S/HC | ||||||
| Reset | 0 | 0 | 0 |
Bit 17 – PREFDIS When CTRLB.CHEDIS==0: When CTRLB.CHEDIS==1: Predictive Prefetch is always disabled and this field is ignored.
When CTRLB.CHEDIS=0:
1 (DISABLE) = Predictive Prefetch Disabled
0 (ENABLE) = Predictive Prefetch Enabled
When CTRLB.CHEDIS=1:
Predictive Prefetch is always disabled and this field is ignored.
| Value | Name | Description |
|---|---|---|
| 1 | DISABLE | Predictive Prefetch Disabled |
| 0 | ENABLE | Predictive Prefetch Enabled |
Bit 16 – CHEDIS Cache Disable
| Value | Name | Description |
|---|---|---|
| 1 | DISABLE | Cache Disabled; Interface uses RDBUFWS selection. |
| 0 | ENABLE | Cache Enabled; Accesses to flash use AUTOWS/FSW selection. |
Bits 9:8 – SLP[1:0] Note: The status of power reduction is reflected in STATUS.PRM.
Note: The status of power reduction
is reflected in STATUS.PRM.
| Value | Name | Description |
|---|---|---|
| 3 | AUTOSLOW | Enter Flash Hibernate on entry to Standby w/ wakeup on first access |
| 2 | AUTOFAST | Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby |
| 1 | RSVD01 | RSVD |
| 0 | MANUAL | Maintain state of STATUS.PRM on entry to Standby |
Bit 7 – CHEINV Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read.
| Value | Name | Description |
|---|---|---|
| 1 | INV | Invalidate Cache |
| 0 | NONE | No Action |
Bit 1 – TEMP When written to 1, this bit remains a 1 until STATUS.TEMP toggles. Then it returns to 0. Note: When changing TEMP, software must adjust CTRLA.FWS appropriately or have CTRLA.AUTOWS==1. Note: The status of Operating Temp Read Mode is reflected in STATUS.TEMP.
| Value | Name | Description |
|---|---|---|
| 1 | TOGGLE | Toggle the Operating Temperature Read Mode |
| 0 | NONE | No Action |
Bit 0 – PRM When written to 1, this bit remains a 1 until STATUS.PRM toggles. Then it returns to 0. Note: The status of power reduction is reflected in STATUS.PRM.
When written to 1, this bit remains a 1 until STATUS.PRM toggles. Then it is cleared by hardware. Writing a 0 has no effect.
Note: The status of power reduction
is reflected in STATUS.PRM.
| Value | Name | Description |
|---|---|---|
| 1 | TOGGLE | Toggle the Flash Power Mode |
| 0 | NONE | No Action |