31.6.28 Write Protection Control REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | WPCTRL |
| Offset: | 0x70 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WPFFLTEN | WPCRCEN | WPLCK | WPEN | ||||||
| Access | R/W | R/W | R/S | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 31:8 – WPKEY[23:0] Writing a value other than FCR_WPCTRL_KEY to this field cancels the write operation this register and generates a slave bus error. This field always returns 0 on read.
Bit 3 – WPFFLTEN Note: FFLTMODE.FLTMD[] selection 001 and 011 which lock the mode will eventually be de-featured since they are redundant with the WPCTRL.WPFFLTEN feature.
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | FFLT Register write protection enabled. Non-debugger writes to FLT registers marked with write protect property are canceled and generate a slave bus error. |
| 0 | DISABLE | FFLT Register write protection disabled. |
Bit 2 – WPCRCEN Write Protection Enable for CRC Registers
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | CRC Register write protection enabled. Non-debugger writes to CRC registers marked with write protect property are canceled and generate a slave bus error. |
| 0 | DISABLE | CRC Register write protection disabled. |
Bit 1 – WPLCK WPCTRL Write LOCK
| Value | Name | Description |
|---|---|---|
| 1 | LOCKED | WPCTRL register is write protected. This bit can only be cleared by a hardware reset. |
| 0 | UNLOCKED | WPCTRL is not write protected. |
Bit 0 – WPEN Note: Write Protection also applies to HSM accesses for this module.
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | Register write protection enabled (for registers not associated with a WP<feature>EN bit). Non-debugger writes to registers marked with write protect property are canceled and generate a slave bus error. |
| 0 | DISABLE | Register write protection disabled. |