31.6.8 Debug Control CTRL REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DBGCTRL |
| Offset: | 0x1c |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DBGECC[1:0] | CRCRUN | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 2:1 – DBGECC[1:0] Debug ECC ModeECC errors from debugger reads are:
ECC errors from debugger reads are:
| Value | Name | Description |
|---|---|---|
| 3 | RSVD11 | Don't use but same as 01 (DISABLE) |
| 2 | ENABLE | Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup. |
| 1 | DISABLE | Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated. |
| 0 | NOERR | Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated. |
Bit 0 – CRCRUN CRC Debug Run Enable
| Value | Name | Description |
|---|---|---|
| 1 | RUN | CRC Logic Runs in Debug Mode. |
| 0 | HALT | CRC Logic Halts in Debug Mode |