31.6.25 Flash ECC Fault Parity REGISTER

Table 31-56. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: FFLTPAR
Offset: 0x60
Reset: 0x00000000
Property: R

Bit 3130292827262524 
 DEDOUT      SECOUT[8] 
Access R/HS/HCR/HS/HC 
Reset 00 
Bit 2322212019181716 
 SECOUT[7:0] 
Access R/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HC 
Reset 00000000 
Bit 15141312111098 
 DEDIN      SECIN[8] 
Access R/HS/HCR/HS/HC 
Reset 00 
Bit 76543210 
 SECIN[7:0] 
Access R/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HCR/HS/HC 
Reset 00000000 

Bit 31 – DEDOUT For Flash Writes this value is based on write data and the calculated SEC Parity bits. For Flash Reads this value is based on read data and the calculated SEC Parity bits. Note: See TableHardSpace2-4 for calculation vector bit order vs data bit order vs control bit order. Note: This document refers to DED, Overall Parity, and Parity[0] interchangeably.

For Writes this value is based on write data and the calculated SEC Parity bits.

For Reads this value is based on read data and the calculated SEC Parity bits.

Note:
  1. See the table for calculation vector bit order vs data bit order vs control bit order.
  2. “DED”, “Overall Parity”, and “Parity[0]” are used interchangeably.

Bits 24:16 – SECOUT[8:0] For Flash Writes this value is based on write data. For Flash Reads this value is based on read data. Condition: {PFM_DATA_MSB==63} SECOUT[8:7] are always 0. Condition: {PFM_DATA_MSB==127} SECOUT[8] is always 0. Condition: {PFM_DATA_MSB==255} All SECOUT bits are used. Note: See TableHardSpace2-4 for calculation vector bit order vs data bit order vs control bit order. Note: The number of active bits is dependent on the data width of the flash panel. Note: This document refers to SECOUT[8:0] and Parity[9:1] interchangeably.

For Writes this value is based on write data.

For Reads this value is based on read data.

Note:
  1. See the table for calculation vector bit order vs data bit order vs control bit order.
  2. SECOUT[8].
  3. The terms “SEC*[8:0]” and “Parity[9:1]” are used interchangeably.

Bit 15 – DEDIN For Flash Writes this value is always 0. For Flash Reads this value is the overall parity read from flash. Note: See TableHardSpace2-4 for calculation vector bit order vs data bit order vs control bit order. Note: This document refers to DED, Overall Parity, and Parity[0] interchangeably.

For Writes this value is always 0.

For Reads this value is the overall parity read from flash.

Note:
  1. See the table for calculation vector bit order vs data bit order vs control bit order.
  2. “DED”, “Overall Parity”, and “Parity[0]” are used interchangeably.

Bits 8:0 – SECIN[8:0] For Flash Writes this value is always 0. For Flash Reads this value is the Single Error Parity bits read from flash. Condition: {PFM_DATA_MSB==63} SECIN[8:7] are always 0. Condition: {PFM_DATA_MSB==127} SECIN[8] is always 0. Condition: {PFM_DATA_MSB==255} All SECIN bits are valid. Note: See TableHardSpace2-4 for calculation vector bit order vs data bit order vs control bit order. Note: The number of active bits is dependent on the data width of the flash panel. Note: This document refers to SECIN[8:0] and Parity[9:1] interchangeably.

For Writes this value is always0.

For Reads this value is the Single Error Parity bits read from Flash.

Note:
  1. See the table for calculation vector bit order vs data bit order vs control bit order.
  2. SECIN[8] is always 0.
  3. The terms “SEC*[8:0]” and “Parity[9:1]” are used interchangeably.