31.6.21 Flash ECC Fault Mode REGISTER

Table 31-52. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 14:12 – FLTMD[2:0] Fault Mode Control

Note: Write Protected when FLTEN = 1.

000 = Fault Injection Disabled

001 = Reserved

010 = Fault Capture Mode Enabled

Capture the address (in FLTADR) and Syndrome in (FLTSYN)

011 =Reserved

100 = Single Fault Injection (at bit selected by FLT1PTR) for Reads

101 = Double Fault Injection for Reads

110 = Single Fault Injection (at bit selected by FLT1PTR) for Writes

111 = Double Fault Injection for Writes

Value	Name	Description
0	DISABLE	Fault Injection Disabled
2	CAPT	Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN)
4	SINGLEREAD	Single Fault Injection (at bit selected by FLT1PTR) for Reads
5	DOUBLEREAD	Double Fault Injection for Reads
6	SINGLEWRITE	Single Fault Injection (at bit selected by FLT1PTR) for Writes
7	DOUBLEWRITE	Double Fault Injection for Writes

Note: Write Protected when FLTEN = 1.

If FLTMD = 1xx and FLTEN = 1:

Value	Name	Description
1		Inject a Fault on to the associated ECC/Parity Control bits (CTL[n])
0		No Fault Injected