31.6.10 CRC Control REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CRCCTRL |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | CRCEN | CRCRST | |||||||
| Access | R/W | R/W/HC | R/S/HC | ||||||
| Reset | 0 | 0 | 0 |
Bit 5 – RUNSTDBY CRC Run in Standby
| Value | Name | Description |
|---|---|---|
| 1 | RUN | CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby) |
| 0 | HALT | CRC Halts in Standby |
Bit 1 – CRCEN When CRCEN = 1, any write to a CRC registers labeled as Enable-Protected is discarded and an error is generated. Note: Hardware clears this bit when CRC operation finishes (i.e. when HW sets INTFLAG.CRCDONE=1).
Note: When CRCEN = 1 all other CRC*
SFR bits are write protected, except CRCEN, CRCRST, and CRCPAUSE.PAUSE
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | CRC Calculation Enabled (w/ start on write to 1). |
| 0 | DISABLE | Stops CRC calculation. |
Bit 0 – CRCRST CRC Reset
| Value | Name | Description |
|---|---|---|
| 1 | RESET | Resets all CRC SFR bits. |
| 0 | NONE | No Action |