31.6.11 CRC MODE REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CRCMODE |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PERIOD[11:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PERIOD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RIN | ROUT | AUTOR | PLEN32 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 27:16 – PERIOD[11:0] The number of PerCLK counts CRC logic waits between needing new data and reading that data from flash. 0x000 = Read Data Immediately 0x001 = Wait 1 PerCLK count + 2 AHB Clocks (for sync) ... 0xFFF = Wait 4095 PerCLK counts + 2 AHB Clocks (for sync)
The number of PerCLK counts CRC logic waits between needing new data and reading that data from flash. (The PerCLK is clock at an 8 MHz fixed frequency. Non-zero PERIOD values are used to throttle back the bandwidth used for CRC calculations.)
0 = Read Data Immediately
All Other Values = Wait PERIOD PerCLK counts + 2 AHB Clocks (for sync) before starting
Bit 15 – RIN This option is sometimes referred to as Reflected Byte or Reflected Input.
This option is sometimes referred to as Reflected Byte or Reflected Input.
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | The LFSR CRC is calculated Least Significant Bit first (Reflected) |
| 0 | DISABLE | The LFSR CRC is calculated Most Significant Bit first (Not Reflected) |
Bit 14 – ROUT This option is sometimes referred to as Reflected Result or Reflected Output.
This option is sometimes referred to as Reflected Result or Reflected Output.
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | The CRCACC is Reflected (before the Final XOR) |
| 0 | DISABLE | The CRCACC is Not Reflected |
Bit 13 – AUTOR CRC Auto Repeat
| Value | Name | Description |
|---|---|---|
| 1 | ENABLE | Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR |
| 0 | DISABLE | Perform CRC calculation once then set DONE and if needed, CRCERR. |
Bit 12 – PLEN32 Polynomial Length Select
| Value | Name | Description |
|---|---|---|
| 1 | THIRTYTWO | Polynomial is 32-bits |
| 0 | SIXTEEN | Polynomial is 16-bits |