31.6.23 Flash ECC Fault Address REGISTER

Bits 27:0 – FLTADR[27:0] If Fault Injection Mode, this is the System Physical Address at which to inject fault(s) Note: Not all bits in this register are writable. FFLTADR[27:24] determines which flash region (CFM, BFM, PFM) is targeted and always exist. For FFLTADR[23:0] only the number of bits required to address the largest flash region (PFM) exists. Bits that don't exist are treated as R-0. Note: If FLTADR is within VSS Page space, FLT logic is disabled. Condition: {PFM_DATA_MSB==63} This is a byte address but aligned to 8 bytes and FLTADR[2:0] are always 0. Condition: {PFM_DATA_MSB==127} This is a byte address but aligned to 16 bytes and FLTADR[3:0] are always 0. Condition: {PFM_DATA_MSB==255} This is a byte address but aligned to 32 bytes and FLTADR[4:0] are always 0.