45.8.28 FIFO level register.

Table 45-29. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: RNG_Control_Registers__FIFOLevel
Offset: 0x11004
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
 FIFOLevel[31:24] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 2322212019181716 
 FIFOLevel[23:16] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 15141312111098 
 FIFOLevel[15:8] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 76543210 
 FIFOLevel[7:0] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 

Bits 31:0 – FIFOLevel[31:0]

Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.