45.8.9

Table 45-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CryptoMaster_DMA_Registers__PUSH_ADDR_MSB
Offset:	0x10014
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	PUSH_ADDR_MSB[31:24]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PUSH_ADDR_MSB[23:16]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PUSH_ADDR_MSB[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PUSH_ADDR_MSB[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – PUSH_ADDR_MSB[31:0] Push Address MSB

Direct mode: This register is written by the software (address of the first data).

Scatter-gather mode: This register is written by software (address of the first descriptor). Afterwards, it is updated by the hardware after each processed descriptor.

32-bit address: The ADDR_LSB register and ADDR_MSB register both give access to the same 32-bit register.

64-bit address: One register gives access to the 32 most significant bits and one register gives access to the 32 least significant bits.