45.8.27 Control register

Table 45-28. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RNG_Control_Registers__Control
Offset:	0x11000
Reset:	0x00040000
Property:	RW


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
				FifoWriteStartUp	Nb128BitBlocks[3:0]
Access				RW	RW	RW	RW	RW
Reset				0	0	1	0	0


Bit	15	14	13	12	11	10	9	8
	AIS31TestSel	HealthTestSel	AIS31Bypass	HealthTestBypass	ForceActiveROs	IntEnAlm	IntEnPre	SoftRst
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	IntEnFull		IntEnProp	IntEnRep	CondBypass	TestEn	LFSREn	Enable
Access	RW		RW	RW	RW	RW	RW	RW
Reset	0		0	0	0	0	0	0

Bit 20 – FifoWriteStartUp

Enable write of the samples in the FIFO during start-up.

Bits 19:16 – Nb128BitBlocks[3:0]

Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.

Bit 15 – AIS31TestSel

Select input to the AIS31 test module: 0: Before conditioning, 1: After conditioning.

Bit 14 – HealthTestSel

Select input to health test module: 0: Before conditioning, 1: After conditioning.

Bit 13 – AIS31Bypass

Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state.

Bit 12 – HealthTestBypass

Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state.

Bit 11 – ForceActiveROs

Force oscillators to run when FIFO is full.

Bit 10 – IntEnAlm

Interrupt enable for AIS31 noise alarm.

Bit 9 – IntEnPre

Interrupt enable for AIS31 preliminary noise alarm.

Bit 8 – SoftRst

Software reset: 0: Normal mode, 1: The continuous test, the conditioning function and the FIFO are reset. This bit is not cleared automatically.

Bit 7 – IntEnFull

Interrupt enable for FIFO full.

Bit 5 – IntEnProp

Interrupt enable for Adaptive Proportion Test failure (1024-sample window).

Bit 4 – IntEnRep

Interrupt enable for Repetition Count Test failure.

Bit 3 – CondBypass

0: the conditioning function is used (normal mode), 1: the conditioning function is bypassed (to observe entropy source directly).

Bit 2 – TestEn

Select input for conditioning function and continuous tests: 0: Noise source (normal mode), 1: Test data register (test mode).

Bit 1 – LFSREn

Select between the NDRNG with asynchronous free running oscillators (when '0') and the Pseudo-Random generator with synchronous oscillators for simulation purpose (when '1').

Bit 0 – Enable

Enable the NDRNG.